The accumulated termination theory of the series becomes concrete inside a charge-management IC: a small device that integrates voltage and temperature acquisition, the multi-criterion termination state machine, programmable timers and the outputs that command the power stage through fast charge, top-off and trickle. The Texas Instruments bq2002 family is the canonical example and remains an instructive reference for how NiMH charge control is hardened into silicon. This paper walks its architecture block by block - inputs, comparators and timers, the termination decision logic, the post-fast-charge phases and status reporting - showing how external resistors configure policy and how the same architecture reappears across modern integrated and MCU-based chargers.
The bq2002/F/G variants are NiCd/NiMH fast-charge controllers that manage a current-limited or constant-current supply through the states of Paper 10: they gate fast charge on battery voltage and temperature qualification, run fast charge, terminate on the first satisfied criterion among -delta-V, rate-of-temperature-rise, maximum voltage, maximum temperature and maximum time, then provide an optional top-off and selectable pulse-trickle maintenance. The device drives the external power stage and a status LED from a compact pin count.
Seeing the state machine in a datasheet grounds the abstract criteria: each termination method is a hardware comparator or timer feeding a common OR-decision, exactly the defence-in-depth logic the earlier papers derive from chemistry.
Battery voltage is acquired through a resistor divider into a voltage-sense pin compared against an internal band-gap reference, giving the maximum-voltage bound and the -delta-V peak-tracking circuitry; temperature enters through an NTC divider whose Vtemp is compared against cold, hot and rate-of-change thresholds (the VTCO/rate-of-rise functions described in NTC fast-charge application notes). Qualification comparators inhibit fast charge until both sensed quantities lie inside their allowed windows.
Because thresholds are derived from a stable reference and resistor-programmed inputs, accuracy depends on divider tolerance and NTC beta/quality - reinforcing the sensor-selection discipline of Paper 7 and the current-stable measurement requirement of Paper 6.
The -delta-V block maintains the peak and detects the programmed per-cell decline, with sampling cadence and confirmation implemented to reject noise; the dT/dt block differentiates Vtemp to catch the recombination-driven rise near 1 C/min; maximum-voltage, maximum-temperature and a programmable maximum-fast-charge-timer run in parallel as independent bounds. Any one satisfied ends fast charge - the OR logic that guarantees coverage when, for example, warmth erases the voltage dip.
Programming pins select chemistry (NiMH versus NiCd thresholds, reflecting NiMH's smaller dip), safety-timer duration and termination options, so the same silicon is configured to a specific pack by a handful of passive components rather than firmware - deterministic and auditable, which suits cost-sensitive and safety-oriented designs.
After fast termination the IC can run a timer-limited top-off at a reduced current to complete cells that terminate slightly before full (Paper 9) - particularly relevant at 1C and C/2 - and then enter a selectable pulse-trickle mode whose duty cycle sets an average maintenance current matched to self-discharge rather than a damaging continuous trickle. These integrated phases mean the complete fast-to-maintain sequence runs without a microcontroller.
The output commands the external power stage's current-set/control pin, so the designer's power topology (Paper 36) translates the IC's state into actual fast, top-off and trickle currents; the IC supplies the decision, the external stage supplies the power.
Status outputs drive LEDs or a host to distinguish charging, full and fault; qualification failures (out-of-window voltage/temperature, sensor fault) inhibit fast charge and indicate the condition rather than charging blindly. In a microcontroller design these same blocks become ADC channels, timer peripherals and firmware state machines, gaining flexibility (logging, adaptive thresholds, multi-chemistry) but inheriting the responsibility to provide an independent watchdog and fail-safe power disable (Paper 10).
The first figure is the IC block architecture; the second sequences how the parallel terminators and the state machine interact across a full charge, the silicon embodiment of the whole termination group.
A reliable implementation follows the datasheet's configuration math for timer and temperature resistors, validates every terminator in a thermal chamber, confirms the power-stage currents match the IC's commanded phases, and keeps the hard maximum-time/temperature paths independent of firmware where possible. Weijiang's cell peak, thermal and timing characterisation supplies the numbers those configuration resistors encode. The next paper zooms into the two measurements the IC depends on most - current sensing and NTC placement.
Weijiang Power designs and manufactures nickel-metal hydride cells, matched packs and charging-ready configurations for consumer, industrial, medical and mobility customers, and supports partners with charge-protocol guidance, IEC 61951-2 performance files, IEC 62133-1 safety evidence and charger co-validation. Share your cell format, charge rate, thermal envelope and cycle target and our engineers will specify a cell-and-charge combination that protects both runtime and service life. Review the range on the products page.
